1. Field of Invention
Various exemplary embodiments generally relate to a semiconductor device and an operating method thereof and, more particularly, to a read operation method of a semiconductor device including a source line voltage detection circuit.
2. Description of Related Art
A semiconductor device includes a plurality of memory cells that store data. The memory cells include normal memory cells storing general data and flag cells storing various types of data necessary for the semiconductor device to operate.
A single level cell (SLC) is a memory cell in which one bit of data is stored. A multi-level cell (MLC) is a memory cell in which two or more bits of data are stored. The single level cell may be divided into an erase state or a program state based on a threshold voltage distribution. The multi-level cell may be divided into an erase state or one of a plurality of program states based on a threshold voltage distribution.
When the multi-level cell is programmed, a least significant bit (LSB) program operation and a most significant bit (MSB) program operation may be performed to reduce the width of the threshold voltage distribution. Data indicating whether the LSB program operation or the MSB program operation is performed (hereinafter, “LSB/MSB completion data”) is stored in the flag cells of each page. A page may refer to a group of memory cells coupled to the same word line.
When LSB/MSB completion data is stored in the flag cells, the LSB/MSB completion data of the flag cells may be read first during a read operation of a page including the flag cells, and it may be determined from the read data whether the LSB program operation or the MSB program operation is completely performed on the page.
However, since each page includes the flag cells storing the LSB/MSB completion data, there is a limit to how much the size of a memory cell array may be reduced.